# Semiconductors, foundries, fabless designers, equipment and capital-intensive hardware — sector playbook

Use this when: the company designs, manufactures, packages, tests, or supplies the tools and materials for integrated circuits — pure-play foundries, fabless designers, IDMs, memory makers, OSAT/ATMP assembly-test houses, wafer-fab-equipment (WFE) vendors, EDA and IP licensors, semiconductor materials suppliers, and the capital-intensive hardware businesses (photonics, power modules, advanced packaging substrates) that share their economics.

Three facts break the generic checklist here, and they compound. First, this is a **fixed-cost manufacturing business layered on a physics roadmap**: the same fab prints 55% gross margin at 95% utilisation and negative margin at 60%, with no change in management quality, product or price discipline. Second, **spending precedes revenue by two to four years** — a fab sanctioned today depreciates for a decade against demand nobody can forecast — so cash flow and returns look worst exactly when a company is investing into a genuine upcycle. Third, the industry runs a violent **inventory cycle stacked on top of a capex cycle**, and demand seen by a chip supplier is the second derivative of end demand: a 5% dip in device sales produces a 30% collapse in orders once the channel destocks. Your job is to separate cycle from franchise, distinguish the depreciation schedule from the business, and to read operational KPIs — utilisation, yield, node mix, channel inventory, book-to-bill — that no financial ratio contains.

## Contents

1. [Why the generic ratio set fails here](#why-the-generic-ratio-set-fails-here)
2. [The metrics that actually matter](#the-metrics-that-actually-matter)
3. [How to value companies in this sector](#how-to-value-companies-in-this-sector)
4. [Peer set construction](#peer-set-construction)
5. [Sector-specific red flags](#sector-specific-red-flags)
6. [Cycle and structural context](#cycle-and-structural-context)
7. [India vs global notes](#india-vs-global-notes)
8. [Checklist](#checklist)

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## Why the generic ratio set fails here

Work through these before quoting any standard ratio. In most cases the correct action is to suppress the metric, or to replace it with the cycle-normalised or business-model-specific version — not to print it with a footnote.

**P/E — inverted across the cycle, and the single most common way to buy the top.** Semiconductor earnings are extraordinarily operationally geared: a 20% revenue decline can take EPS down 60–80% because depreciation, fab fixed costs and R&D are all committed. So the stock screens at 6–9x on peak earnings just as the correction begins, and at 40x, 80x or a loss at the trough when risk-reward is best. For memory, foundry and WFE this inversion is near-total. **Treat a mid-single-digit P/E on record earnings as a warning, not a valuation.** Only mid-cycle normalised EPS makes a P/E interpretable, and for memory it barely does even then. Mature-node analog and microcontroller businesses, and EDA/IP licensors, are the exceptions where trailing P/E carries real information.

**OPM and gross margin — largely a utilisation and depreciation artifact, not a measure of pricing power.** Fab operating leverage is brutal: incremental gross margin on marginal wafers is often 70–90% because the fab is already paid for. A foundry at 95% utilisation and one at 65% utilisation with identical technology, cost discipline and pricing will print margins 20+ points apart. Comparing OPM across a foundry, a fabless designer (no fab depreciation, but full R&D and third-party wafer cost), an OSAT (thin margin, high asset turns) and an EDA vendor is a category error — the numbers are not measuring the same thing. Decompose margin into **utilisation, node/product mix, yield, ASP and depreciation load** before attributing any of it to management.

**EV/EBITDA — actively misleading for anyone who owns a fab, and the most dangerous multiple in the sector.** EBITDA adds back depreciation, but for a foundry, memory maker or IDM, depreciation *is* the business: capacity physically obsoletes on a node cadence and must be rebuilt continuously. A leading-edge fab running 15–35% of revenue as capex year after year converts a "6x EV/EBITDA" into something closer to fair or expensive on any cash measure. Use **EV/(EBITDA − maintenance capex)**, EV/EBIT, or EV/FCF with a normalised capex assumption. EV/EBITDA is defensible for fabless designers and EDA companies, where D&A is small and mostly acquisition-related.

**FCF — correctly signed for fabless, mis-signed for anyone building capacity.** A foundry sanctioning two fabs into a genuine structural upcycle will show deeply negative FCF for three years; that is the investment thesis executing, not distress. Conversely, a fab owner harvesting — cutting capex below depreciation, skipping the node transition — prints beautiful FCF for two or three years while its competitive position erodes irreversibly, because you cannot re-enter a node you skipped. **Always split capex into maintenance/technology-upgrade versus greenfield capacity, compare capex to depreciation, and treat capex < D&A for multiple years at a leading-edge manufacturer as a red flag rather than a quality signal.** For fabless firms, FCF is a clean and central metric — there is no fab to hide behind.

**ROCE / ROIC — distorted by the depreciation cycle in both directions, and non-comparable across models.** A fully depreciated 200mm mature-node fab shows spectacular ROCE on a near-zero denominator; a just-commissioned 300mm fab shows negative ROCE while capital sits in CWIP producing nothing. Neither number describes the economics. Compound this with government capex subsidies (which under some regimes net off the asset's carrying value, permanently inflating measured returns), acquisition goodwill on the fabless side, and capitalised versus expensed development. Compute ROIC on **mid-cycle EBIT** and, for manufacturers, sanity-check against **replacement cost of installed capacity** rather than net book. For fabless designers, ROCE is nearly meaningless — the real capital is expensed R&D, so invested capital is understated and returns look absurdly high.

**P/B — near-useless for fabless, genuinely informative for manufacturers.** A fabless designer's principal asset is a decade of expensed R&D, an IP library and a customer socket base, none of which is on the balance sheet; P/B of 15–25x says nothing. For memory makers and foundries, however, book value approximates replaceable physical capacity, and **P/B has historically been one of the more reliable cycle-timing tools** — troughs cluster near or below 1x for memory, peaks well above.

**D/E and net debt/EBITDA — procyclical and structurally incomplete.** Leverage looks safe on peak EBITDA and terrifying on identical debt at the trough; always test against **trough EBITDA**. More importantly, the reported debt figure routinely misses the real obligations: multi-year take-or-pay wafer supply agreements, customer capacity prepayments received (a liability, and sometimes a disguised financing), equipment purchase commitments already placed with 12–18 month lead times, operating leases on tools and buildings, and non-cancellable long-term materials contracts. Read the commitments and contingencies note before forming a leverage view.

**Current ratio and working-capital rules — contaminated by prepayments and deliberate inventory build.** Customer prepayments (common in shortages) sit in current liabilities and crush the current ratio while representing the opposite of stress. Equipment vendors carry huge customer deposits and deferred revenue for the same reason. Meanwhile a company can *strategically* build inventory ahead of a ramp or in anticipation of export restrictions — the ratio deteriorates, the business is fine. Never read the current ratio here without reading the composition.

**Revenue growth as reported — often measures channel behaviour, not demand.** Most broad-based analog, MCU and discrete suppliers sell into distributors and recognise revenue on **sell-in** (shipment to distributor) or **sell-through** (distributor's onward sale), and firms change convention. A quarter of "growth" can be pure channel fill, and a quarter of collapse can be pure destocking with end demand flat. Reconcile reported revenue against distributor weeks-of-inventory and, where disclosed, sell-through, before attributing growth to demand.

**Non-GAAP EPS — the sector's standard presentation, and it excludes real costs.** Fabless and EDA companies routinely exclude stock-based compensation (which can run 10–25% of revenue and is a genuine, recurring, dilutive expense) and acquisition-related intangible amortisation (real for a serial acquirer). Use GAAP as the base; if you use non-GAAP, add SBC back and track **net dilution after buybacks** — many buyback programmes are simply funding dilution, not returning capital.

**Backlog and "design win pipeline" — quoted as if contracted, frequently not.** Semiconductor backlog is often cancellable, and during shortages customers double- and triple-order across suppliers, inflating backlog with phantom demand that vanishes without a single cancellation notice. A design win is an *option* on revenue, not revenue: it converts 12–36 months later, at volumes the customer controls, and can be lost at the next platform refresh.

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## The metrics that actually matter

Ranges below are **indicative only**. They vary by sub-sector, node, geography, cycle position and reporting period, and several are conventions that drift. A company's own history across a full cycle, and its direct sub-sector peers at the *same point in the cycle*, always override any absolute band quoted here.

| Metric | Definition / how to compute | Indicative healthy range | Why it matters |
|---|---|---|---|
| **Fab utilisation rate** | Actual wafer starts ÷ installed capacity, ideally by fab and node. Rarely disclosed directly outside foundries and Japanese/Taiwanese IDMs; infer from wafer shipments vs stated capacity, from gross margin bridges in the concall, or from management's qualitative "loadings" commentary. | Above 90% is a tight, profitable market; 80–90% workable; below 70–75% typically means gross margin compression of 10+ points and is the classic downcycle signature. Mature-node specialty fabs often run structurally lower. | The single largest short-run driver of margin for anyone who owns a fab, and it is an *operational* variable no financial ratio contains. Utilisation explains most quarter-to-quarter margin surprise; attributing that surprise to pricing or cost control is almost always wrong. |
| **Capex intensity** | Capex ÷ revenue, split into (a) maintenance and technology upgrade, (b) greenfield capacity, (c) advanced packaging. Compare with D&A. | Leading-edge foundry/memory: 30–45% at the top of an investment cycle, high-teens to 25% mid-cycle. Mature-node/specialty: 10–15%. OSAT: 15–25%. Fabless: 1–3%. Equipment/EDA: 2–5%. **Capex sustained below D&A at a leading-edge manufacturer is under-investment, not efficiency.** | Determines both future capacity (revenue) and future depreciation (cost), on a 2–4 year lag. It is the sector's core capital-allocation decision and the main destroyer of returns: capacity sanctioned at the top arrives at the trough. Track the *ratio to depreciation* over five years — that is the harvesting-vs-investing test. |
| **Depreciation as % of revenue, and depreciation policy** | D&A ÷ revenue; plus the assumed useful life of fab equipment disclosed in the accounting policy note. | Foundry/memory: 20–35% of revenue. Fabless: below 5% ex-acquisition amortisation. Equipment lives of 5 years are conservative; extensions to 6, 7 or 8 years should be flagged and quantified. | Depreciation is the largest fixed cost in a fab and it front-loads: a new fab is loss-making for 4–8 quarters purely on depreciation before yields mature. Extending useful life is a legitimate accounting choice for mature-node tools and a classic earnings-flattering lever at the leading edge — **always quantify the EPS effect of any life extension and restate to the prior policy.** |
| **Wafer starts per month (WSPM), on 300mm-equivalent basis** | Installed capacity in 8-inch or 12-inch equivalents; convert (one 300mm wafer ≈ 2.25x the area of a 200mm). Track capacity growth vs shipment growth. | Judge against the company's own trajectory and announced fab ramps rather than an absolute. Capacity growing materially faster than shipments for more than 2–3 quarters presages a utilisation and margin problem. | The physical unit of the industry. Capacity is added in indivisible fab-sized lumps with 24–36 month lead times, which is *why* the industry over- and under-shoots. Revenue forecasts that are not reconcilable to wafer capacity are unanchored. |
| **Blended wafer ASP / revenue per wafer** | Wafer revenue ÷ wafers shipped (12-inch equivalent). Decompose into node mix and price. | Rising blended ASP driven by *mix* toward advanced nodes is healthy; rising ASP purely from price during a shortage is a reversal risk. Flat volumes with falling ASP is the destocking signature. | Separates genuine technology migration from cyclical pricing. A foundry whose ASP rises only because it raised prices in a shortage will give it all back; one whose ASP rises because 3nm replaced 7nm has moved up the value chain permanently. |
| **Revenue by process node (advanced-node mix)** | % of wafer revenue from ≤7nm, ≤5nm, ≤3nm (leading edge) vs 16/28nm (mainstream) vs ≥40nm (mature/specialty). Disclosed by foundries; inferable for IDMs. | For a leading-edge foundry, a rising and majority share from the two newest nodes. For a specialty player, node mix is irrelevant — judge on BCD/BiCMOS/SiC/GaN/RF/power differentiation instead. | The node roadmap *is* the competitive position at the leading edge. Only two or three players can fund each successive node; falling behind by one node is usually terminal for the merchant business because the leading customers migrate and do not come back. Conversely, mature-node economics are about differentiation and fab depreciation status, not nanometres — do not penalise a specialty fab for lacking 3nm. |
| **Yield / defect density (D0) and yield-ramp trajectory** | Defect density per cm²; or good die per wafer ÷ gross die per wafer. Rarely disclosed numerically — infer from gross margin trajectory during a ramp, from management's "yield is ahead of/behind plan" language, and from customer commentary. | A new node typically starts at 30–60% yield and reaches mature yield (often 80–90%+ for moderate die sizes) over 4–8 quarters. Faster-than-plan ramps show up as gross margin beating guidance during a ramp quarter. | Yield determines cost per good die and therefore whether a node is profitable at all. A node that ramps slowly burns depreciation against low output, and yield problems are the most common cause of a manufacturer losing a socket to a competitor mid-generation. **Large die (GPUs, HBM-attached logic) are disproportionately yield-sensitive — defect probability scales with die area.** |
| **Cost per good die** | (Wafer cost + test + packaging) ÷ (gross die per wafer × yield). Gross die per wafer falls with die area; yield falls faster. | Judge as a trend within a product family and against the prior node. **Node shrinks no longer reliably reduce cost per transistor** — below ~7nm, wafer cost inflation (EUV, multi-patterning, mask sets) has largely offset density gains for many designs. | This is the real unit economic, and it is why the industry pivoted to chiplets and advanced packaging. A company whose roadmap assumes classical cost-per-transistor scaling is planning on an economics that stopped holding. Also explains why mature nodes remain highly profitable rather than obsolete. |
| **Inventory days — own and channel (the full pipeline)** | Own DOI = inventory ÷ COGS × 365, split into raw/WIP/finished goods. Plus **distributor weeks of inventory** and, where available, sell-in vs sell-through gap. Add customer inventory commentary. | Own DOI: fabless 60–100 days; IDM/analog 90–130 days (they run deliberately high to serve long product lifecycles); foundry 60–90. Distributor: 7–9 weeks is normal, 12+ weeks is a correction in progress. | **This is the single best early-warning indicator in the sector.** Inventory accumulates in three places — supplier, distributor, customer — and a correction is the simultaneous drain of all three. Rising own FG inventory plus rising channel weeks plus flat end demand is the canonical pre-correction setup, and it precedes the revenue decline by one to three quarters. Rising *raw and WIP* inventory ahead of a disclosed ramp is a different and benign signal. |
| **Book-to-bill and WFE spend trajectory** (equipment and materials) | Orders booked ÷ revenue billed in the period; plus disclosed backlog and its coverage in months; plus the industry WFE spend forecast (SEMI, and the majors' own guidance). | Above 1.0 sustained = expansion; below 0.9 for two or more quarters = contraction underway. Backlog coverage of 6–12 months is normal for WFE. | Equipment revenue is the derivative of foundry/memory capex, which is itself the derivative of chip demand — so WFE amplitude is the largest in the value chain (peak-to-trough swings of 30–40% in a normal cycle). Book-to-bill turns before revenue and is the cleanest leading indicator available. Discount backlog for cancellability and for push-outs, which is how customers actually cut without cancelling. |
| **R&D intensity** | R&D ÷ revenue. For fabless, also R&D per major design win and mask-set/tape-out cost exposure. | Fabless logic/compute: 20–35%. Analog/mixed-signal: 12–18%. Foundry: 7–9%. Memory: 8–12%. OSAT: 3–6%. EDA/IP: 30–40%. **Falling R&D intensity in a downturn at a leading-edge player is a solvency-driven decision with multi-year consequences.** | R&D is the true capex of a fabless company and is fully expensed, which is why its ROCE is meaningless and its book value is fictional. Node economics make this a scale business: a leading-edge SoC tape-out can cost tens to hundreds of millions of dollars before a single unit ships, so sub-scale players cannot participate at all. Track R&D in absolute currency through the cycle, not just as a ratio — the ratio rises in a downturn on falling revenue while spending is actually being cut. |
| **Customer concentration** | Revenue from top-1 and top-5 customers. US filers must disclose any customer above 10% of revenue (ASC 280); Ind-AS 108 requires equivalent disclosure. Also check end-market concentration behind the direct customer. | Top-5 above 50%, or any single customer above 20%, is a structural risk that should affect the discount rate, not just be noted. Foundries and OSATs routinely exceed this and are still investable — but only where the customer is captive to the technology. | Sockets are large, few, and multi-year. Losing one designed-in flagship socket can remove 15–30% of revenue in a single product cycle with no warning in the financials until it happens. Concentration cuts both ways: a customer that cannot switch (because of process, IP or packaging lock-in) is a moat; a customer that dual-sources or is building its own silicon is a countdown. |
| **Design wins and socket longevity** | Number and value of design wins; the design-win-to-revenue lag; expected product lifecycle; and share of revenue from products older than 5 years. | Design-win-to-revenue lag: consumer 9–18 months, industrial 2–3 years, automotive 3–5 years. Automotive/industrial sockets then run 7–15 years; consumer sockets 12–24 months. | Determines the persistence of revenue and therefore the multiple. An automotive analog supplier with 10-year sockets and 30-year-old parts still shipping deserves a completely different valuation from a consumer SoC vendor re-competing for its entire revenue base every 18 months. **Check the vintage of the revenue base, not just the growth rate.** |
| **Free cash flow after capex, through a full cycle** | FCF = CFO − capex, averaged over a complete 4–5 year cycle and separately at the peak and trough. | Fabless: 20–35% FCF margin mid-cycle. Leading-edge manufacturers: positive on a cycle average but frequently negative for 2–3 consecutive years during a build. Memory: negative at trough is normal. | The only capital-allocation test that survives the depreciation and utilisation distortions. Single-year FCF is nearly uninterpretable here; **cycle-average FCF versus cycle-average capex tells you whether the business actually earns its cost of capital or merely converts shareholder money into fabs.** Several historically respected manufacturers have never cleared this bar. |
| **Government incentives and effective net capex** | Grants, investment tax credits and subsidised loans received or committed, and their accounting treatment (netted against the asset's cost vs recognised as deferred income and released to P&L). | Announced support of 25–50% of project cost is now common globally. What matters is cash received vs announced, and the clawback/milestone conditions. | Subsidies materially change project IRR and can permanently distort reported ROCE — netting a grant off the asset both lowers the denominator and lowers future depreciation, flattering returns for a decade. **Restate returns on gross, pre-subsidy capital cost to compare a subsidised project with an unsubsidised peer.** Also check whether subsidy receipt is conditional on volumes, employment or milestones the company may miss. |
| **Export-control and geographic revenue exposure** | Revenue and capacity by country of end use; share of revenue requiring export licences; share of manufacturing concentrated in a single geography. | Not a range — a mapping. Flag any single-country manufacturing above ~60% of capacity, and any restricted-market revenue above ~15–20%. | Regulatory action can remove a revenue line at a stroke with no commercial warning, and has repeatedly done so. Geographic concentration of leading-edge capacity is an unhedgeable tail risk that belongs in the discount rate or in an explicit scenario, not in a footnote. |

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## How to value companies in this sector

**Start by placing the cycle, then choose the method.** Never quote a multiple before stating where you believe the silicon cycle, the memory cycle and the WFE cycle are — they are related but not synchronous, and the answer changes which method is valid.

**Fabless designers (logic, SoC, analog, RF, connectivity).** Cash-generative, asset-light, R&D-driven. Use **EV/Sales cross-checked against a growth-and-margin frame** (the classic anchor: a rough sum of revenue growth % and FCF margin %, compared across the peer set), **EV/FCF**, and **P/E on mid-cycle EPS**. A DCF is defensible with an explicit cycle in the forecast years — never straight-line a peak year into perpetuity. Always value on **GAAP** earnings or add SBC back; and use fully diluted share count including unvested awards.

**Pure-play foundries and IDMs with fabs.** Use **EV/EBIT** or **EV/(EBITDA − maintenance capex)**, **P/B against ROE** (book value here is real, replaceable capacity), and **EV per 12-inch-equivalent wafer of installed capacity against greenfield replacement cost** — a leading-edge fab's build cost is a genuine valuation floor and a barrier-to-entry measure at once. A DCF works only if capex is modelled as permanently high and cyclical, with explicit node transitions; the terminal value must assume continuing reinvestment at roughly depreciation-plus, not a harvest.

**Memory (DRAM, NAND, HBM).** The most commodity-like sub-sector: undifferentiated bits, price set by supply/demand balance, oligopoly discipline that periodically breaks. Value on **P/B through the cycle** (troughs historically near or below 1x book, peaks well above) and on **mid-cycle EPS**, never on trailing P/E, which is fully inverted. Model bit supply growth versus bit demand growth explicitly — that ratio, not any financial metric, sets the price. HBM is a partial exception: it is capacity-constrained, contracted ahead, and behaves more like a specialty logic product, so segment it out.

**Wafer fab equipment and materials.** Revenue is the derivative of customer capex, so amplitude is the highest in the chain. Value on **mid-cycle EPS × a through-cycle multiple**, and cross-check with **EV/Sales against normalised WFE spend**. Give explicit credit for the **installed-base / service and spares revenue**, which is recurring, high-margin and far less cyclical than tool sales — valuing it at the same multiple as tool revenue undervalues the better business. **Do not extrapolate a peak-capex year.**

**OSAT / ATMP (assembly, test, packaging).** Capital-intensive, thinner margin, closer to contract manufacturing. Use **EV/EBITDA net of maintenance capex**, ROCE against WACC, and capacity utilisation. Advanced packaging (2.5D/3D, CoWoS-class, fan-out, chiplet integration) commands genuinely better economics than commodity wire-bond and must be segmented separately.

**EDA and semiconductor IP licensors.** These are software/royalty businesses wearing a semiconductor label. Value them as such: **recurring revenue, backlog/RPO, net revenue retention, Rule-of-40 style frames, EV/FCF, DCF on royalty streams.** They are the least cyclical link in the chain because design activity continues through a downturn.

**What NOT to use.** Trailing P/E for anything cyclical here (inverted). Trailing EV/EBITDA for a fab owner (ignores the mandatory reinvestment that *is* the cost structure). PEG on a cyclical peak (the "G" is a cycle, not a trend). Dividend discount models (payouts are residual and subordinate to capex). Book-value screens for fabless firms (the assets are expensed). Perpetual-growth DCF terminal values without explicit ongoing capex at or above depreciation. And do not use a single point estimate at all — **present bear/mid/bull across a cycle scenario**, because the honest uncertainty here is a range, not a number.

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## Peer set construction

A valid comparable shares **business model, position on the node/technology curve, end market, and cycle exposure**. The word "semiconductor" is not a peer set — it spans businesses with 3% capex intensity and 40% capex intensity.

**Splits that must never be mixed:**

- **Fabless vs foundry vs IDM vs OSAT vs equipment vs EDA/IP vs materials vs distributor.** Different capital intensity, different margin structure, different position in the cycle, different multiples. Mixing them makes every ratio comparison meaningless.
- **Leading edge vs mature/specialty node.** A ≤5nm foundry and a 180nm BCD/power specialty fab are in different industries. The first competes on R&D scale and roadmap; the second on differentiated process, fully depreciated tools and customer stickiness.
- **Logic vs memory vs analog/mixed-signal vs discrete/power vs sensors.** Memory is a commodity with a bit-price cycle; analog is a long-tail catalogue business with 10-year sockets and structurally high, stable margins; compute logic is a winner-take-most design race.
- **End market: AI/datacentre vs smartphone vs PC vs automotive vs industrial vs consumer.** These cycles are not synchronised and have diverged sharply — one can be at a record while another is in a deep correction. A "semis peer group" spanning both produces an average that describes nobody.
- **Silicon vs compound semiconductors (SiC, GaN, GaAs, InP).** Different substrates, different cost curves, different maturity, and a different competitive dynamic (substrate supply, not lithography).
- **Merchant vs captive.** A company selling into the open market is not comparable to one whose output is largely consumed by an affiliate or a single anchor customer at negotiated transfer prices.

**Additional dimensions to hold constant:** geography of manufacturing (subsidy regime, labour and utility cost, export-control exposure), stage of ramp (a company mid-fab-ramp is not comparable to one at steady state), and subsidy treatment (compare returns pre-subsidy).

**Cycle synchronisation is mandatory.** Comparing a company reporting a trough quarter with one reporting a peak quarter produces a conclusion about calendars, not businesses. If the peer set is not at the same cycle point, normalise everything to mid-cycle before comparing.

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## Sector-specific red flags

**Channel stuffing and the sell-in/sell-through gap.** Revenue recognised on shipment to distributors while distributor inventory weeks climb is borrowed revenue that reverses violently. Watch for: distributor weeks rising while revenue grows; a change in revenue recognition convention; extended payment terms or expanded return/price-protection rights; and receivables growing materially faster than revenue. This is the most common way a semiconductor company delays admitting a correction.

**Depreciation-life extensions and reclassification.** Extending fab equipment life from 5 to 6+ years, or moving tools between asset classes, lifts EPS with zero cash effect. Legitimate for genuinely long-lived mature-node tools; a warning sign at the leading edge. Quantify the EPS impact and restate.

**Capex falling below depreciation for multiple years at a manufacturer.** Reads as excellent FCF and is usually a decision to skip or delay a node. It is close to irreversible — re-entering a node you sat out requires both capital and a customer base that has already migrated.

**Capitalising costs that should be expensed.** Pre-production fab costs, ramp-up losses, and development spend capitalised into CWIP or intangibles; also watch for prolonged accumulation in capital work-in-progress without transfer to fixed assets, which defers depreciation. Under Ind-AS 38 / IAS 38, development capitalisation is permitted on criteria; check whether a peer group expenses the same spend.

**Non-GAAP that excludes recurring items.** SBC, acquisition amortisation, "ramp-up costs", "restructuring" that recurs annually, and inventory write-downs that later reverse into margin as the written-down stock is sold (which inflates a future quarter's gross margin — a real and recurring pattern worth checking after any large write-down).

**Backlog and order-book inflation.** Double-ordering across suppliers during shortages, non-cancellable-in-name-only agreements, and "long-term supply agreements" or customer prepayments presented as demand certainty. Ask what happens to the LTA if the customer's end demand halves — usually it is renegotiated.

**Design-win language substituting for revenue.** Companies late in a socket cycle emphasise pipeline, wins and "engagements" precisely when converting revenue is weakening. Check the lag: if wins announced three years ago have not become revenue, they will not.

**Single-socket dependency being quietly lost.** The signals are subtle and lead the financials: a customer announcing in-house silicon, a competitor's win at the same customer, declining share of a customer's bill of materials, or the supplier moving from sole- to dual-source. None of this appears in the accounts until the revenue is gone.

**Yield problems disguised as mix.** Gross margin missing guidance during a ramp, attributed to "product mix", when the real cause is a slow yield curve on a new node. Cross-check with customer commentary and with whether the ramp schedule slipped.

**Government-grant dependency and clawbacks.** A project whose IRR only works with subsidy, milestone conditions that may be missed, grants announced but not received, and grant accounting that flatters ROCE. Check the cash flow statement for actual receipts against announced amounts.

**Inventory write-down asymmetry.** Large write-downs at the trough (understating cost) followed by sale of that inventory at zero cost basis (overstating recovery margins). Normalise gross margin across both periods.

**India-specific.** Companies re-badging themselves as "semiconductor" plays with no fab, no ATMP line and no chip revenue — verify the actual revenue mix and whether an announced MoU has converted into a signed agreement, a land allotment, disbursed incentive, and equipment orders. Also check promoter pledge, related-party technology-licence and royalty payments to an overseas partner, CARO comments on capital advances and CWIP, and whether announced capacity is a policy application or a funded project.

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## Cycle and structural context

**The silicon cycle.** Historically 3–4 years peak to peak, driven by the mismatch between capacity added in 24–36 month lumps and demand that moves continuously. The classical sequence: lead times extend → customers over-order and build safety stock → suppliers read the double-ordering as demand and add capacity → end demand normalises → channel destocks → shipments fall far below consumption → utilisation and margins collapse → capex is cut → the next shortage. **Lead times and distributor inventory weeks turn before revenue; revenue turns before earnings; earnings turn before the multiple re-rates.** Know which of these you are looking at.

**The inventory correction specifically.** Corrections are amplification events, not demand events. Because the channel holds several weeks of stock and customers hold their own, a modest slowdown in end demand produces a disproportionate collapse in supplier shipments while the pipeline drains, then a disproportionate snap-back when it refills. **Do not model a correction as a demand forecast** — model the pipeline. The reliable trough signal is inventory days normalising across supplier, distributor and customer simultaneously, plus lead times bottoming, not an improvement in reported earnings.

**The WFE cycle rides on top and swings harder.** Equipment orders are the derivative of customer capex plans, so a 15% cut in foundry capex can mean a 30%+ decline in tool orders, and the reverse on the way up. Book-to-bill is the leading indicator. Service and installed-base revenue is the shock absorber.

**Memory runs its own cycle.** Bit supply growth (from both new fabs and node migration, which yields more bits from the same wafers) against bit demand growth sets price, and price moves multiples in both directions. Oligopoly discipline moderates the amplitude but has broken repeatedly.

**Structural: node economics have changed.** Cost per transistor no longer falls reliably with each shrink; EUV tools, multi-patterning, mask sets and design costs have risen faster than density gains for many designs. The industry response — chiplets, 2.5D/3D advanced packaging, heterogeneous integration — moves value toward packaging and toward whoever controls the interconnect. Consequence: **advanced packaging capacity is now a genuine bottleneck and a valuation driver in its own right**, and mature nodes remain highly profitable rather than obsolete.

**Structural: customer disintermediation.** Large end-customers (hyperscalers, handset and auto OEMs) increasingly design their own silicon and buy foundry capacity directly. This is good for foundries and packaging, bad for merchant chip vendors selling into those same accounts. Check whether a company's largest customer is also a prospective competitor.

**Structural: AI demand concentration.** A large share of recent industry growth is concentrated in datacentre accelerators, HBM and the advanced packaging and networking around them, funded by a small number of buyers. That concentration is both the growth story and the principal risk: a capex pause at a handful of customers propagates through the entire leading-edge chain. Treat it as a scenario, not a trend line.

**Regulation and geopolitics.** Export controls on advanced compute, lithography tools and, increasingly, on manufacturing equipment and design software, are now a first-order determinant of addressable market and can change without commercial warning. Entity-list additions, licence requirements, foreign direct product rules, outbound investment screening and tariffs all bear directly on revenue. Simultaneously, large subsidy programmes (US, EU, Japan, Korea, China, India) are deliberately building duplicative capacity, which is supportive for equipment vendors and a medium-term oversupply risk for manufacturers, especially at mature nodes. **Geographic concentration of leading-edge capacity in a single strait-adjacent region is an unhedgeable tail risk** — handle it explicitly in scenarios rather than by ignoring it.

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## India vs global notes

**The listed universe is different from the global one — check what the company actually does.** India currently has no operating leading-edge logic fab. The listed "semiconductor" exposure is overwhelmingly: chip *design services* and VLSI engineering (people businesses, valued like IT services — headcount, utilisation, billing rate, attrition, not wafer economics), EMS and PCB assembly (contract manufacturing economics), power/discrete and packaging aspirants, and equipment/materials suppliers. **Apply the design-services or EMS frame to those, not this one.** Reserve this playbook for genuine fab, ATMP/OSAT and semiconductor-materials businesses.

**Policy framework (India-specific).** The India Semiconductor Mission provides fiscal support of up to 50% of project cost for fabs, display fabs, compound-semiconductor/ATMP/OSAT units, with state governments layering additional support; the Design Linked Incentive scheme supports design companies on a smaller scale. For any company citing these: verify approval status, the actual disbursement schedule, milestone and employment conditions, clawback provisions, and how much has been received in cash versus announced. An approval is not a fab.

**Accounting (Ind-AS).** Government grants follow **Ind-AS 20** — an entity may present a capital grant either as deferred income released to P&L over the asset's life or as a deduction from the asset's carrying amount. The second materially inflates reported ROCE for a decade. **Identify the policy and restate to gross cost for comparability with global peers.** Development-cost capitalisation under Ind-AS 38 mirrors IAS 38; check it against peer treatment. Leases under Ind-AS 116 bring tool and building leases on balance sheet. Watch capital work-in-progress ageing disclosures (Schedule III requires a CWIP ageing and completion schedule) — prolonged CWIP with slipping completion dates is a direct read on project execution.

**Disclosure gaps (India).** Indian filings rarely disclose fab utilisation, wafer starts, yield, node mix, book-to-bill or channel inventory. You will often have to reconstruct these from the concall transcript, the annual report's management discussion, capacity tables in the directors' report, and industry sources. **If a KPI is unavailable, say so explicitly rather than substituting a financial ratio for it.** Concalls are the richest source of operational commentary; read the Q&A, not just the prepared remarks.

**India-specific governance items.** Promoter holding and pledge levels; related-party transactions, especially technology licences, royalty and off-take arrangements with an overseas technology partner (common in Indian fab and ATMP joint ventures — check whether the royalty is arm's-length and whether it scales with volume); CARO 2020 reporting on capital advances, loans to related parties and use of borrowed funds; and the gap between announced MoUs and signed, funded, land-allotted, equipment-ordered projects. Figures are in crore/lakh — normalise before any cross-border comparison, and state the INR/USD rate used.

**Global filings (US/EU/Asia).** US 10-K/10-Q under GAAP via EDGAR: expect segment reporting (ASC 280) including disclosure of any customer above 10% of revenue, extensive risk factors on export controls and concentration, and detailed commitments notes covering purchase obligations and capacity agreements. Taiwanese, Korean and Japanese manufacturers disclose **monthly revenue**, which is the highest-frequency real-time cycle indicator available anywhere in the sector — use it. Foundries and equipment makers also disclose capacity, utilisation commentary, node-mix revenue splits and capex guidance in quarterly decks that have no Indian equivalent. IFRS filers under IAS 20 face the same grant-presentation choice as Ind-AS filers; check it the same way.

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## Checklist

- [ ] State where the silicon, memory and WFE cycles each are, and on what evidence, before quoting a single multiple.
- [ ] Classify the business model precisely — fabless / foundry / IDM / OSAT / equipment / EDA-IP / materials / design services — and apply the right frame.
- [ ] Suppress trailing P/E for cyclical sub-sectors, or show it only next to mid-cycle normalised EPS.
- [ ] Do not use EV/EBITDA for any company that owns a fab; use EV/EBIT or EV/(EBITDA − maintenance capex).
- [ ] Decompose gross margin into utilisation, node/product mix, yield, ASP and depreciation load before attributing it to management.
- [ ] Find or infer fab utilisation; flag anything below ~75% as a margin event in progress.
- [ ] Compute capex ÷ revenue and capex ÷ D&A over five years; flag capex below depreciation at a leading-edge manufacturer.
- [ ] Split capex into maintenance/upgrade versus greenfield capacity versus advanced packaging.
- [ ] Read the depreciation policy note; quantify and restate any useful-life extension.
- [ ] Track wafer starts / installed capacity against shipment growth; capacity outrunning shipments presages a utilisation problem.
- [ ] Compute blended wafer ASP and separate mix-driven gains from shortage pricing.
- [ ] Check advanced-node revenue mix and roadmap credibility; for specialty fabs, judge differentiation instead of nanometres.
- [ ] Look for yield-ramp evidence in gross margin bridges and ramp-quarter guidance misses.
- [ ] Compute own inventory days split by raw/WIP/FG, and obtain distributor weeks of inventory and the sell-in/sell-through convention.
- [ ] For equipment and materials names, get book-to-bill, backlog coverage, push-out commentary and installed-base/service revenue share.
- [ ] Track R&D in absolute currency through the cycle, not only as a percentage of revenue.
- [ ] Identify top-1 and top-5 customer concentration and assess switching cost and in-house-silicon risk at each.
- [ ] Establish design-win-to-revenue lag, socket life and the share of revenue from products older than five years.
- [ ] Compute cycle-average FCF versus cycle-average capex — the real test of whether the business earns its cost of capital.
- [ ] Use GAAP earnings; add SBC back to any non-GAAP figure and check net dilution after buybacks.
- [ ] Identify all government grants, their accounting treatment, cash actually received, and clawback conditions; restate ROCE pre-subsidy.
- [ ] Map revenue and manufacturing capacity by geography; quantify export-control-restricted revenue explicitly.
- [ ] Read commitments and contingencies for take-or-pay wafer agreements, equipment purchase orders and customer prepayments before forming a leverage view.
- [ ] Test leverage against trough EBITDA, not trailing.
- [ ] Build the peer set on business model, node position, end market and cycle point — never on the "semiconductor" label.
- [ ] India: verify the company actually has fab/ATMP revenue rather than an MoU; check ISM/DLI disbursement status, Ind-AS 20 grant presentation, CWIP ageing, promoter pledge and related-party royalty terms.
- [ ] Global: use monthly revenue disclosures from Taiwanese/Korean/Japanese filers as the highest-frequency cycle read available.
- [ ] Present the conclusion as bear/mid/bull across a cycle scenario, not as a single target price.
